The present invention relates to a technique for reducing power consumption of a processor system which includes a plurality of processors of the same type or different types such as processing units called a central processing unit (CPU), a hardware engine (HWE), a coprocessor or a digital signal processor (DSP) and is capable of performing parallel processing.
There has been a known technique for reducing power consumption of a CPU by lowering the frequency of a clock signal when the load in processing of the CPU is light (e.g., Japanese Unexamined Patent Publication No. 9-34599.) Also known is a technique for reducing power consumption and heat release of/from an entire system by turning off a power source of an associated unit when a decoded instruction is “no-operation” in a processor system including a plurality of units such as a CPU and a coprocessor (e.g., Japanese Unexamined Patent Publication No. 2000-112756.)
Also known is a technique for enhancing the processing ability or reducing power consumption by controlling the number of CPUs operating at the same time in accordance with the processing load or the setting of an operation environment (e.g., Japanese Unexamined Patent Publication No. 9-138716.)
The above-mentioned technique of merely reducing the frequency of a clock signal is applicable when the processing load is light, but is not applicable when a high processing ability is required. Therefore, large reduction of power consumption of an entire system is not always achieved.
In addition, with the technique of turning off a power source for a unit which does not perform processing, power consumption in processing itself is not reduced, and thus large reduction of power consumption is not achieved as well.
Moreover, the technique of controlling the number of CPUs operating at the same time cannot reduce power consumption when a high processing ability is required, so that enhancement of the processing ability and reduction of power consumption are not achieved at the same time.